<p>Kevin Cheng has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20305">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/fizz: Add audio devices<br><br>- Describe RT5663 headphone codec in ACPI so it can<br>be enumerated by the OS.<br><br>- Supply NHLT binaries for RT5663<br><br>BUT=b:62872377<br>TEST=Apply full patch set and UCM, verify basic audio works.<br><br>Signed-off-by: Kevin Cheng <kevin.cheng@intel.com><br>Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076<br>---<br>M src/mainboard/google/fizz/Kconfig<br>M src/mainboard/google/fizz/devicetree.cb<br>M src/mainboard/google/fizz/gpio.h<br>M src/mainboard/google/fizz/mainboard.c<br>4 files changed, 45 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20305/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig<br>index e15d229..107af9a 100644<br>--- a/src/mainboard/google/fizz/Kconfig<br>+++ b/src/mainboard/google/fizz/Kconfig<br>@@ -83,4 +83,8 @@<br> int<br> default 64 # GPE0_DW2_00 (GPP_E0)<br> <br>+config INCLUDE_NHLT_BLOBS<br>+ bool "Include blobs for audio."<br>+ select NHLT_RT5663<br>+<br> endif<br>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb<br>index f1d2b77..a493de5 100644<br>--- a/src/mainboard/google/fizz/devicetree.cb<br>+++ b/src/mainboard/google/fizz/devicetree.cb<br>@@ -245,6 +245,13 @@<br> device pci 17.0 on end # SATA<br> device pci 19.0 on end # UART #2<br> device pci 19.1 on<br>+ chip drivers/i2c/generic<br>+ register "hid" = ""10EC5663""<br>+ register "name" = ""RT53""<br>+ register "desc" = ""Realtek RT5663""<br>+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"<br>+ device i2c 13 on end<br>+ end<br> end # I2C #5<br> device pci 19.2 off end # I2C #4<br> device pci 1c.0 on end # PCI Express Port 1<br>diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h<br>index 56324b5..13081ec 100644<br>--- a/src/mainboard/google/fizz/gpio.h<br>+++ b/src/mainboard/google/fizz/gpio.h<br>@@ -143,8 +143,8 @@<br> /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),<br> /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),<br> /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),<br>-/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE,<br>- PLTRST), /* HP_IRQ_GPIO */<br>+/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,<br>+ PLTRST, EDGE), /* HP_IRQ_GPIO */<br> /* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10),<br> /* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),<br> /* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),<br>diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c<br>index 1f6dc87c..a925f08 100644<br>--- a/src/mainboard/google/fizz/mainboard.c<br>+++ b/src/mainboard/google/fizz/mainboard.c<br>@@ -18,11 +18,41 @@<br> #include <device/device.h><br> #include <ec/ec.h><br> #include <soc/pci_devs.h><br>+#include <soc/nhlt.h><br> #include <vendorcode/google/chromeos/chromeos.h><br>+<br>+static const char *oem_id = "GOOGLE";<br>+static const char *oem_table_id = "FIZZ";<br> <br> static void mainboard_init(device_t dev)<br> {<br> mainboard_ec_init();<br>+}<br>+<br>+static unsigned long mainboard_write_acpi_tables(<br>+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)<br>+{<br>+ uintptr_t start_addr;<br>+ uintptr_t end_addr;<br>+ struct nhlt *nhlt;<br>+<br>+ start_addr = current;<br>+<br>+ nhlt = nhlt_init();<br>+ if (!nhlt)<br>+ return start_addr;<br>+<br>+ /* RT5663 Headset codec */<br>+ if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1))<br>+ printk(BIOS_ERR, "Couldn't add headset codec.\n");<br>+<br>+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,<br>+ oem_id, oem_table_id, 0);<br>+<br>+ if (end_addr != start_addr)<br>+ acpi_add_table(rsdp, (void *)start_addr);<br>+<br>+ return end_addr;<br> }<br> <br> static void mainboard_enable(device_t dev)<br>@@ -44,6 +74,8 @@<br> if (tpm)<br> tpm->enabled = 0;<br> }<br>+<br>+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;<br> }<br> <br> struct chip_operations mainboard_ops = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20305">change 20305</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20305"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076 </div>
<div style="display:none"> Gerrit-Change-Number: 20305 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kevin Cheng <kevin.cheng@intel.com> </div>