<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20275">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add gnvs<br><br>Add ACPI asl for global non-volitile storage (gnvs).<br><br>Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f<br>Signed-off-by: Marc Jones <marc.jones@scarletltd.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>R src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/acpi/cpu.asl<br>A src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>M src/soc/amd/stoneyridge/acpi/lpc.asl<br>A src/soc/amd/stoneyridge/include/soc/acpi.h<br>A src/soc/amd/stoneyridge/include/soc/nvs.h<br>M src/soc/amd/stoneyridge/lpc.c<br>8 files changed, 216 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/20275/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index c48f53a..fdcb57c 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -61,7 +61,7 @@<br> <br> ramstage-y += chip.c<br> ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c<br>-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c<br>+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br> ramstage-y += fixme.c<br> ramstage-y += gpio.c<br> ramstage-y += hda.c<br>diff --git a/src/soc/amd/stoneyridge/fadt.c b/src/soc/amd/stoneyridge/acpi.c<br>similarity index 84%<br>rename from src/soc/amd/stoneyridge/fadt.c<br>rename to src/soc/amd/stoneyridge/acpi.c<br>index fb3410c..34164f4 100644<br>--- a/src/soc/amd/stoneyridge/fadt.c<br>+++ b/src/soc/amd/stoneyridge/acpi.c<br>@@ -1,7 +1,8 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2014 Google Inc.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -20,20 +21,15 @@<br> #include <string.h><br> #include <console/console.h><br> #include <arch/acpi.h><br>+#include <arch/acpigen.h><br> #include <arch/io.h><br>+#include <cbmem.h><br> #include <device/device.h><br>+#include <soc/acpi.h><br> #include <soc/hudson.h><br>+#include <soc/nvs.h><br> #include <soc/smi.h><br> <br>-#if CONFIG_STONEYRIDGE_LEGACY_FREE<br>- #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE<br>-#else<br>- #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)<br>-#endif<br>-<br>-#ifndef FADT_PM_PROFILE<br>- #define FADT_PM_PROFILE PM_UNSPECIFIED<br>-#endif<br> <br> /*<br> * Reference section 5.2.9 Fixed ACPI Description Table (FADT)<br>@@ -205,3 +201,53 @@<br> <br> header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));<br> }<br>+<br>+unsigned long southbridge_write_acpi_tables(device_t device,<br>+ unsigned long current,<br>+ struct acpi_rsdp *rsdp)<br>+{<br>+ return acpi_write_hpet(device, current, rsdp);<br>+}<br>+<br>+static void acpi_create_gnvs(struct global_nvs_t *gnvs)<br>+{<br>+ /* Clear out GNVS. */<br>+ memset(gnvs, 0, sizeof(*gnvs));<br>+<br>+ if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))<br>+ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);<br>+<br>+ if (IS_ENABLED(CONFIG_CHROMEOS)) {<br>+ /* Initialize Verified Boot data */<br>+ chromeos_init_vboot(&gnvs->chromeos);<br>+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;<br>+ }<br>+<br>+ /* Set unknown wake source */<br>+ gnvs->pm1i = ~0ULL;<br>+<br>+ /* CPU core count */<br>+ gnvs->pcnt = dev_count_cpu();<br>+}<br>+<br>+void southbridge_inject_dsdt(device_t device)<br>+{<br>+ struct global_nvs_t *gnvs;<br>+<br>+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+ if (!gnvs) {<br>+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));<br>+ if (gnvs)<br>+ memset(gnvs, 0, sizeof(*gnvs));<br>+ }<br>+<br>+ if (gnvs) {<br>+ acpi_create_gnvs(gnvs);<br>+ acpi_save_gnvs((uintptr_t)gnvs);<br>+<br>+ /* Add it to DSDT. */<br>+ acpigen_write_scope("\\");<br>+ acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);<br>+ acpigen_pop_len();<br>+ }<br>+}<br>diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl<br>index aae3287..32dad76 100644<br>--- a/src/soc/amd/stoneyridge/acpi/cpu.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl<br>@@ -13,14 +13,18 @@<br> * GNU General Public License for more details.<br> */<br> <br>+/* Required function by EC, Notify OS to re-read CPU tables */<br>+Method (PNOT)<br>+{<br>+}<br>+<br> /*<br> * Processor Object<br>- *<br> */<br> Scope (\_PR) { /* define processor scope */<br> Processor(<br> P000, /* name space name */<br>- 0, /* Unique number for this processor */<br>+ 0, /* Unique number for this processor */<br> 0x810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br>@@ -28,49 +32,49 @@<br> <br> Processor(<br> P001, /* name space name */<br>- 1, /* Unique number for this processor */<br>+ 1, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P002, /* name space name */<br>- 2, /* Unique number for this processor */<br>+ 2, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P003, /* name space name */<br>- 3, /* Unique number for this processor */<br>+ 3, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P004, /* name space name */<br>- 4, /* Unique number for this processor */<br>+ 4, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P005, /* name space name */<br>- 5, /* Unique number for this processor */<br>+ 5, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P006, /* name space name */<br>- 6, /* Unique number for this processor */<br>+ 6, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br> }<br> Processor(<br> P007, /* name space name */<br>- 7, /* Unique number for this processor */<br>+ 7, /* Unique number for this processor */<br> 0x0810, /* PBLK system I/O address !hardcoded! */<br> 0x06 /* PBLKLEN for boot processor */<br> ) {<br>diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>new file mode 100644<br>index 0000000..bf0ed55<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>@@ -0,0 +1,47 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corp.<br>+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * NOTE: The layout of the GNVS structure below must match the layout in<br>+ * soc/amd/stoneyridge/include/soc/nvs.h !!!<br>+ *<br>+ */<br>+<br>+External (NVSA)<br>+<br>+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)<br>+Field (GNVS, ByteAcc, NoLock, Preserve)<br>+{<br>+ /* Miscellaneous */<br>+ Offset (0x00),<br>+ PCNT, 8, // 0x00 - Processor Count<br>+ PPCM, 8, // 0x01 - Max PPC State<br>+ LIDS, 8, // 0x02 - LID State<br>+ PWRS, 8, // 0x03 - AC Power State<br>+ DPTE, 8, // 0x04 - Enable DPTF<br>+ CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console<br>+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index<br>+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source<br>+ NHLA, 64, // 0x19 - 0x20 - NHLT Address<br>+ NHLL, 32, // 0x21 - 0x24 - NHLT Length<br>+ PRT0, 32, // 0x25 - 0x28 - PERST_0 Address<br>+ SCDP, 8, // 0x29 - SD_CD GPIO portid<br>+ SCDO, 8, // 0x2A - GPIO pad offset relative to the community<br>+ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */<br>+ Offset (0x100),<br>+ #include <vendorcode/google/chromeos/acpi/gnvs.asl><br>+}<br>diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl<br>index 783a2c9..821f669 100644<br>--- a/src/soc/amd/stoneyridge/acpi/lpc.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/lpc.asl<br>@@ -14,8 +14,9 @@<br> */<br> <br> /* 0:14.3 - LPC */<br>-Device(LIBR) {<br>+Device(LPCB) {<br> Name(_ADR, 0x00140003)<br>+<br> /* Method(_INI) {<br> * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")<br> } */ /* End Method(_SB.SBRDG._INI) */<br>@@ -37,7 +38,7 @@<br> )<br> })<br> <br>- Method(_CRS,0,NotSerialized)<br>+ Method(_CRS,0,Serialized)<br> {<br> CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address<br> CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length<br>@@ -100,4 +101,9 @@<br> IRQNoFlags(){13}<br> })<br> } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */<br>+<br>+<br>+ #include "acpi/ec.asl"<br>+ #include "acpi/superio.asl"<br>+<br> } /* end LIBR */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h<br>new file mode 100644<br>index 0000000..ff3e874<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h<br>@@ -0,0 +1,38 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corp.<br>+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_STONEYRIDGE_ACPI_H_<br>+#define _SOC_STONEYRIDGE_ACPI_H_<br>+<br>+#include <arch/acpi.h><br>+<br>+#if CONFIG_STONEYRIDGE_LEGACY_FREE<br>+ #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE<br>+#else<br>+ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)<br>+#endif<br>+<br>+#ifndef FADT_PM_PROFILE<br>+ #define FADT_PM_PROFILE PM_UNSPECIFIED<br>+#endif<br>+<br>+unsigned long southbridge_write_acpi_tables(device_t device,<br>+ unsigned long current, struct acpi_rsdp *rsdp);<br>+<br>+void southbridge_inject_dsdt(device_t device);<br>+<br>+#endif /* _SOC_STONEYRIDGE_ACPI_H_ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h<br>new file mode 100644<br>index 0000000..3ce6faf<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h<br>@@ -0,0 +1,50 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Intel Corp.<br>+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * NOTE: The layout of the global_nvs_t structure below must match the layout<br>+ * in soc/intel/apollolake/acpi/globalnvs.asl !!!<br>+ *<br>+ */<br>+<br>+#ifndef _SOC_STONEYRIDGE_NVS_H_<br>+#define _SOC_STONEYRIDGE_NVS_H_<br>+<br>+#include <vendorcode/google/chromeos/gnvs.h><br>+<br>+typedef struct global_nvs_t {<br>+ /* Miscellaneous */<br>+ uint8_t pcnt; /* 0x00 - Processor Count */<br>+ uint8_t ppcm; /* 0x01 - Max PPC State */<br>+ uint8_t lids; /* 0x02 - LID State */<br>+ uint8_t pwrs; /* 0x03 - AC Power State */<br>+ uint8_t dpte; /* 0x04 - Enable DPTF */<br>+ uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */<br>+ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */<br>+ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */<br>+ uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */<br>+ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */<br>+ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */<br>+ uint8_t scdp; /* 0x29 - SD_CD GPIO portid */<br>+ uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */<br>+ uint8_t unused[213];<br>+<br>+ /* ChromeOS specific (0x100 - 0xfff) */<br>+ chromeos_acpi_t chromeos;<br>+} __attribute__((packed)) global_nvs_t;<br>+<br>+#endif /* _SOC_STONEYRIDGE_NVS_H_ */<br>diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c<br>index 64a4e65..b9abbdc 100644<br>--- a/src/soc/amd/stoneyridge/lpc.c<br>+++ b/src/soc/amd/stoneyridge/lpc.c<br>@@ -28,6 +28,7 @@<br> #include <arch/acpi.h><br> #include <pc80/i8254.h><br> #include <pc80/i8259.h><br>+#include <soc/acpi.h><br> #include <soc/pci_devs.h><br> #include <soc/hudson.h><br> #include <vboot/vbnv.h><br>@@ -356,9 +357,8 @@<br> .read_resources = hudson_lpc_read_resources,<br> .set_resources = hudson_lpc_set_resources,<br> .enable_resources = hudson_lpc_enable_resources,<br>-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br>- .write_acpi_tables = acpi_write_hpet,<br>-#endif<br>+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,<br>+ .write_acpi_tables = southbridge_write_acpi_tables,<br> .init = lpc_init,<br> .scan_bus = scan_lpc_bus,<br> .ops_pci = &lops_pci,<br></pre><p>To view, visit <a href="https://review.coreboot.org/20275">change 20275</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20275"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f </div>
<div style="display:none"> Gerrit-Change-Number: 20275 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>