You know how you see messages about writing to missing registers like these:
OS 9.2] Trying to write invalid spr 0 (0x000) at 00f113c0 11:26:23.910 WARNING [Mac OS 9.2] Trying to read invalid spr 0 (0x000) at 00f113c8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.055 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558 11:26:24.204 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.205 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.205 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558
Should these registers be implemented? Maybe Apple expected these registers to be available on their hardware.
Using these files: http://www.nxp.com/files/32bit/doc/ref_manual/MPC7450UM.pdf page 1-36 and http://www.nxp.com/files/32bit/doc/data_sheet/MPC604.pdf page 19, as a guide, here is what I found out:
SPR Name
944 Monitor Control Register 2 951 Breakpoint Address Mask Register1 955 Sampled Instruction Address 1 959 Sampled Data Address * PowerPC 604 only
My current theory is there might be implementation details that are off in QEMU's emulated PowerPC 750 processor. The only way I know how to test this out is run QEMU in KVM mode on PowerPC hardware. I'm hoping someone out there has this setup available and can tell us if Mac OS 9.2 works better in KVM mode or not.
On Mon, May 02, 2016 at 06:05:05PM -0400, Programmingkid wrote:
You know how you see messages about writing to missing registers like these:
OS 9.2] Trying to write invalid spr 0 (0x000) at 00f113c0 11:26:23.910 WARNING [Mac OS 9.2] Trying to read invalid spr 0 (0x000) at 00f113c8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.055 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558 11:26:24.204 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.205 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.205 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558
Should these registers be implemented? Maybe Apple expected these registers to be available on their hardware.
It is probing if the hardware has these registers here. Nothing is wrong. We discussed this on irc for the gsoc thing...
944 Monitor Control Register 2 951 Breakpoint Address Mask Register1 955 Sampled Instruction Address 1 959 Sampled Data Address * PowerPC 604 only
944 = MMCR2 951 = BAMR 955 = SIAR 959 = SDAR (not just 604, fwiw -- where did you read that?)
Yes. And 0 is MQ (a 601 thing), etc.
Some CPUs have slightly different names for the same thing (prefer SIA to SIAR, etc.; some have different things at the same SPR #. What OS9 is doing here isn't exactly correct, but it is what it is.
Segher
On May 2, 2016, at 6:53 PM, Segher Boessenkool wrote:
On Mon, May 02, 2016 at 06:05:05PM -0400, Programmingkid wrote:
You know how you see messages about writing to missing registers like these:
OS 9.2] Trying to write invalid spr 0 (0x000) at 00f113c0 11:26:23.910 WARNING [Mac OS 9.2] Trying to read invalid spr 0 (0x000) at 00f113c8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.055 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.055 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.056 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.056 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558 11:26:24.204 WARNING [Mac OS 9.2] Trying to write privileged spr 955 (0x3bb) at 00f164b8 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 959 (0x3bf) at 00f16520 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 959 (0x3bf) at 00f16528 11:26:24.204 WARNING [Mac OS 9.2] Trying to write invalid spr 944 (0x3b0) at 00f1653c 11:26:24.204 WARNING [Mac OS 9.2] Trying to read invalid spr 944 (0x3b0) at 00f16544 11:26:24.205 WARNING [Mac OS 9.2] Trying to write invalid spr 951 (0x3b7) at 00f16550 11:26:24.205 WARNING [Mac OS 9.2] Trying to read invalid spr 951 (0x3b7) at 00f16558
Should these registers be implemented? Maybe Apple expected these registers to be available on their hardware.
It is probing if the hardware has these registers here. Nothing is wrong. We discussed this on irc for the gsoc thing...
944 Monitor Control Register 2 951 Breakpoint Address Mask Register1 955 Sampled Instruction Address 1 959 Sampled Data Address * PowerPC 604 only
944 = MMCR2 951 = BAMR 955 = SIAR 959 = SDAR (not just 604, fwiw -- where did you read that?)
http://www.nxp.com/files/32bit/doc/data_sheet/MPC604.pdf page 19
What is says: 604-specific—not defined by the PowerPC architecture
Yes. And 0 is MQ (a 601 thing), etc.
Some CPUs have slightly different names for the same thing (prefer SIA to SIAR, etc.; some have different things at the same SPR #. What OS9 is doing here isn't exactly correct, but it is what it is.
Thank you very much for clearing this up. I have a feeling what Apple did was not what the specifications would prefer.
On Mon, May 02, 2016 at 06:58:43PM -0400, Programmingkid wrote:
959 Sampled Data Address * PowerPC 604 only
944 = MMCR2 951 = BAMR 955 = SIAR 959 = SDAR (not just 604, fwiw -- where did you read that?)
http://www.nxp.com/files/32bit/doc/data_sheet/MPC604.pdf page 19
What is says: 604-specific—not defined by the PowerPC architecture
That's not the same as "604 only" :-)
Segher
On Mon, May 02, 2016 at 06:25:25PM -0500, Segher Boessenkool wrote:
On Mon, May 02, 2016 at 06:58:43PM -0400, Programmingkid wrote:
959 Sampled Data Address * PowerPC 604 only
944 = MMCR2 951 = BAMR 955 = SIAR 959 = SDAR (not just 604, fwiw -- where did you read that?)
http://www.nxp.com/files/32bit/doc/data_sheet/MPC604.pdf page 19
What is says: 604-specific—not defined by the PowerPC architecture
That's not the same as "604 only" :-)
Certainly page 59 of https://fail0verflow.com/media/files/ppc_750cl.pdf says the 750CL does not implement that register, but will allow writes to it without exception for compatibility reasons. Certainly makes it sound like a number of models might implement it. Same for 750GX.
On Mon, May 02, 2016 at 10:47:17PM -0400, Lennart Sorensen wrote:
Certainly page 59 of https://fail0verflow.com/media/files/ppc_750cl.pdf says the 750CL does not implement that register, but will allow writes to it without exception for compatibility reasons. Certainly makes it sound like a number of models might implement it. Same for 750GX.
All 750 (including 7400/7410) have a dummy register there, yeah (but 7450 etc. do not). All those work with OS9 of course (and all that code works properly in QEMU, we have checked -- it is much more than those few printf's show).
Segher
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Lennart Sorensen -
Programmingkid -
Segher Boessenkool