coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

Re: [coreboot] Corboot on IPC-FP4-DP G Series
by Kyösti Mälkki 27 Feb '17

27 Feb '17

On Fri, Feb 17, 2017 at 12:03 AM, giuseppe.ferrigni--- via coreboot < coreboot(a)coreboot.org> wrote: > Hi, > > I'm trying to flash corboot on a IPC-FP4-DP G Series. The system has the > following components (from CPU-Z software tool): > > CPU: AMD GX-224IJ - 00670F00 - Prairie Falcon (Family 15h Model 70h - > Stoney Ridge) > MOTHERBOARD: Gardenia CRB > CHIPSET: AMD K15IMC > SOUTHBRIDGE: Carrizo FCH > LPCIO: Fintek F81803 > > It seems that the actual coreboot release is compatible with each > component, so I configured it as in the attached file. > Obviously, nothing is so simple. After flashing, nothing on video, nothing > on COM port. > I have now some simple questions: > - is my configuration correct? > - how can I start debugging, since I have no feedback? > - Can I test the boot process of the rom in some way using qemu? > - How can I know if the COM ports are connected to the APU or to the > superIO? Which is the right configuration in the first case and in the > second one? > I would check twice the PSP firmware files you have embedded in your image. Unfortunately I cannot give you any SHA sums of correct files to have, but I would assume 3rdparty/blobs has working ones. There is board-status output of a tested configuration for amd/gardenia here: https://www.coreboot.org/Supported_Motherboards#amd.2Fgardenia Kyösti

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ApolloLake Oxbohill CRB GRUB2 menu on serial Console
by Gailu Singh 27 Feb '17

27 Feb '17

Hi Experts, I have built grub2 with coreboot platform support (./configure --with-platform=coreboot) and managed to load it as elf payload in coreboot. I have added terminal support in grub configuration coreboot.cfg as follows serial --speed=115200 --unit=0 --word=8 --parity=no --stop=1 terminal_input --append serial terminal_output --append serial terminal_input --append usb_keyboard #add keyboard support. menuentry 'Boot From Hard Disk (Linux)' { insmod (cbfsdisk)/ahci.mod linux (ahci1,msdos1)/boot/bzImage root=/dev/sda1 resume=/dev/sda5 console=ttyS0,115200 } While I see coreboot logs on serial console, I do not see grub2 menu on serial console. I can see grub2 menu on HDMI display though, however my USB keyboard is not working so not able to control grub either through display or serial console. Any help is appreciated. Thanks

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Raminit fails when using different dimm-speeds on coreboot
by i1w5d7gf38keg＠tutanota.com 26 Feb '17

26 Feb '17

In oem bios there was never a problem with such a configuration. In coreboot there is a problem on gm45 chipsets (thinkpads) and on g41 chipsets. The computer hangs at this point: ... End rcven Done rcven Wrote ones, Read: [0x00000000]=0xffffffff Wrote zeros, Read: [0x00000000]=0x00000000 Wrote ones, Read: [0x00001000]=0xffffffff Wrote zeros, Read: [0x00001000]=0x00000000 Wrote ones, Read: [0x00002000]=0xffffffff Wrote zeros, Read: [0x00002000]=0x00000000 Wrote ones, Read: [0x00003000]=0xffffffff Wrote zeros, Read: [0x00003000]=0x00000000 Wrote ones, Read: [0x08000000]=0xffffffff Wrote zeros, Read: [0x08000000]=0x00000000 Wrote ones, Read: [0x08001000]=0xffffffff Wrote zeros, Read: [0x08001000]=0x00000000 Wrote ones, Read: [0x08002000]=0xffffffff Wrote zeros, Read: [0x08002000]=0x00000000 Wrote ones, Read: [0x08003000]=0xffffffff Wrote zeros, Read: [0x08003000]=0x00000000 Wrote ones, Read: [0x20000000]=0xffffffff Wrote zeros, Read: [0x20000000]=0x00000000 Wrote ones, Read: [0x20001000]=0xffffffff Wrote zeros, Read: [0x20001000]=0x00000000 Wrote ones, Read: [0x20002000]=0xffffffff Wrote zeros, Read: [0x20002000]=0x00000000 Wrote ones, Read: [0x20003000]=0xffffffff Wrote zeros, Read: [0x20003000]=0x00000000 Done dummy reads Total memory: 1024 + 512 = 1536MiB Done DRADRB Done memory map Done enhanced mode Done PRCOMP Done power settings Done ddr2 RAM initialization finished. Memory initialized Done Egress Port Done DMI setup CBMEM: IMD: root @ 5bbff000 254 entries. This happens always for me when i add at bank 1 the faster DDR-DIMM and on the second bank the lower speed one. To use two different speed DDR2-DIMMS in for example g41m-es2l you have to install it the slower one into bank 1 and the faster one into bank 2. Then it boots fine. This can always be reproduced. On latest libreboot binary and on latest coreboot git.

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Freeze after few bootups
by i1w5d7gf38keg＠tutanota.com 26 Feb '17

26 Feb '17

Hardware: gigabyte g41m-es2l, coreboot git, seabios-git, native vga I have the problem that the computer is freezing after few boots. Its hanging then at every boot in this stage: .... tWR: 5 tRFC: 35 tWTR: 4 tRRD: 3 tRTP: 4 Channel 0 possiblynot in self refresh Channel 1 possiblynot in self refresh Done clk crossing Done launch Done timings DimmA populated onlyin channel 0 No dimms in channel1 Done ODT Done pre-jedec MRS... CH0: Found Rank 0 Nothing happens afterwards. I replaced the RAM to an other one. Turned it on, it then reset once: .... tRAS: 18 tRP: 6 tRCD: 6 tWR: 6 tRFC: 51 tWTR: 4 tRRD: 3 tRTP: 4 Reset... and hangs again at this stage: ... Done ODT Done pre-jedec MRS... CH0: Found Rank 0 I disconnected the PSU, removed the CMOS battery and wait few minutes. Then it stops hanging at this stage. I had this problem also on an other g41m-es2l mainboard with latest libreboot image installed. So it does not seem to be hardware related and not fixed in latest coreboot. Anything i could do to help fixing this bug?

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ACPI S3 and S0ix (S0i3)
by Paul Menzel 26 Feb '17

26 Feb '17

Dear coreboot folks, Recently in Linux and coreboot, support for the “S0ix states” [1] is introduced. > S0ix-states represent the residency in the Intel® SoC idle standby > power states. The S0ix states shut off part of the SoC when they are > not in use. The S0ix states are triggered when specific conditions > within the SoC have been achieved, for example: certain components > are in low power states. The SoC consumes the least amount of power > in the deepest (for example, S0i3) state. > > On Linux*, Android*, and Chrome* OS, ACPI-SState represent the > system’s residency in the ACPI Suspend-To-RAM (S3). In the Suspend- > To-RAM state, the Linux kernel powers down many of the systems’ > components while maintaining the system’s state in its main memory. > The system consumes the least amount of power possible while in the > Suspend-To-RAM state. Note that any wakelock will prevent the system > from entering the Suspend-To-RAM state. Microsoft Windows calls this *Connected Standby* [2], and I think supports this since 2013 or 2014. If I understand it correctly, the motivation is to decrease time to “wake-up”, and also to keep the device always connected to the network. As some devices still draw a little power compared to ACPI S3, the power usage during S0i3 is a little higher. Is at least the first item needed with coreboot? The Google Veyron_jaq Chromebook (Medion AKOYA S2013) I have, is done resuming as soon the lid if fully opened. Depending on the WLAN, I believe it’s also reconnected quite fast. Is Chrome OS going to use the new S0i3 over S3 in the future? Thanks, Paul [1] https://software.intel.com/en-us/node/544551 [2] https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/f46fc046-91bf…

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Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
by Andrey Petrov 25 Feb '17

25 Feb '17

On 02/25/2017 11:52 AM, Gailu Singh wrote: > Thank you once again for your help and support. > > Managed to build the coreboot 16MB image with FSP, ifwi and > descriptor.bin and flashed it on the board. When power-on board, I see > Red LED (DS3B1) is ON that seems to be some error. User guide only > provide description of 4 LEDs (DS6B1, DS2C1, DS6B2, D5L1) so I assume > red led is indicating some error condition. > > Currently: > DS6B1 : Green ON > DS6B2 : Green ON > DS2C1 : OFF > DS3B1 : RED ON > > No Output on serial console or HDMI. Red light is never a good sign. Do you have a way to know if PLTRST# has been de-asserted? Another thing is that when you stitch with FIT you need to turn off boot guard completely. I suspect you have it on and that makes CSE to check signatures. Please check that in Platform protection -> Bootguard configuration it is set to "bootguard profile 0 - legacy". Then try restitching fit image and rebuilding coreboot again. - Andrey

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Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
by Andrey Petrov 25 Feb '17

25 Feb '17

On 02/25/2017 11:05 AM, Gailu Singh wrote: > Thanks Andrey, > > Manage to extract required blob with SplitFspBin.py.' I have prebuilt > IFWI binary. only missing part is to find/generate correct > descriptor.bin. > just dd if=fitimage.bin bs=4096 count=1 of=descriptor.bin where fitimage.bin is output from FIT tool. -Andrey

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Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
by Andrey Petrov 25 Feb '17

25 Feb '17

On 02/25/2017 02:48 AM, Gailu Singh wrote: > >>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp. > > >>Please usehttps://review.coreboot.org/#/c/18479/3 as starting point. > >>That is for Leafhill. But once you apply that patch, select mainboard > >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated > >>location and 'make' should give you flashable coreboot.rom. > I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files? You need to use script to break the big blob into smaller blobs: https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/SplitFspBi… $ SplitFspBin.py split FSP.fd Here is some video on FSP2.0 and what blobs does what: https://www.youtube.com/watch?v=uzfiTiP9dEM&feature=youtu.be Here is formal FSP2.0 spec: http://www.intel.com/content/www/us/en/embedded/software/fsp/fsp-architectu… Best, Andrey

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Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
by Zoran Stojsavljevic 25 Feb '17

25 Feb '17

> I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about > the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know > how to create required FSP blob from FSP.bsf and FSP.fd files? FSP-M: MRC code FSP-S: Silicon init code > I have built coreboot image for Apollo Lake and trying to boot Oxbohill CRB but no console or display at HDMI port. Good Luck with your build! ;-) Zoran PS. Tiho, Andrei. Potihon6ky, ponjatno. Esli M(R)C zametit6 tebja, koecto mozet slucitsja, esli on tebja (prezde vsego) NE pozvolil hozjataistvovat6 zdes6. ;-) Elki Palki (Kopalki)! Udaci! Zoran On Sat, Feb 25, 2017 at 11:48 AM, Gailu Singh <gailu96(a)gmail.com> wrote: > >>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp. > > >>Please use https://review.coreboot.org/#/c/18479/3 as starting point. > >>That is for Leafhill. But once you apply that patch, select mainboard > >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated > >>location and 'make' should give you flashable coreboot.rom. > > > I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files? > > > > On Sat, Feb 25, 2017 at 10:49 AM, Gailu Singh <gailu96(a)gmail.com> wrote: > >> Hi Experts, >> >> I have built coreboot image for Apollo Lake and trying to boot Oxbohill >> CRB but no console or display at HDMI port. >> >> My coreboot.rom details >> >> Name Offset Type Size >> cbfs master header 0x0 cbfs header 32 >> fallback/romstage 0x80 stage 28268 >> cpu_microcode_blob.bin 0x6f40 microcode 0 >> fallback/ramstage 0x6fc0 stage 65343 >> config 0x16f40 raw 291 >> revision 0x170c0 raw 569 >> fallback/postcar 0x17340 stage 16916 >> fallback/dsdt.aml 0x1b5c0 raw 99 >> fallback/payload 0x1b680 payload 361265 >> (empty) 0x73a00 null 443544 >> mrc.cache 0xdfec0 mrc_cache 65536 >> (empty) 0xeff00 null 32664 >> bootblock 0xf7ec0 bootblock 32768 >> >> This is an 8 MB image, I flashed it to SPI flash at address 0. When I >> boot the board no output is observed either on USB serial console or on >> HDMI display. >> >> Do I need to add something more to see at least coreboot log. I am tryng >> to use GRUB2 as payload to coreboot. >> >> Thanks >> >> > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Coreboot at Apollo Lake Oxbohill CRB
by Gailu Singh 25 Feb '17

25 Feb '17

>>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp. >>Please use https://review.coreboot.org/#/c/18479/3 as starting point. >>That is for Leafhill. But once you apply that patch, select mainboard >>intel/leafhill in 'make nconfig', put the sacred blobs in the designated >>location and 'make' should give you flashable coreboot.rom. I pulled the leafhill patches and yes I get options to specify FSP when selected leafhill. However not clear about the difference between FSP-M.fv and FSP-S.fv. I have FSP.bsf and FSP.fd files for FSP. Can you please let me know how to create required FSP blob from FSP.bsf and FSP.fd files? On Sat, Feb 25, 2017 at 10:49 AM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Experts, > > I have built coreboot image for Apollo Lake and trying to boot Oxbohill > CRB but no console or display at HDMI port. > > My coreboot.rom details > > Name Offset Type Size > cbfs master header 0x0 cbfs header 32 > fallback/romstage 0x80 stage 28268 > cpu_microcode_blob.bin 0x6f40 microcode 0 > fallback/ramstage 0x6fc0 stage 65343 > config 0x16f40 raw 291 > revision 0x170c0 raw 569 > fallback/postcar 0x17340 stage 16916 > fallback/dsdt.aml 0x1b5c0 raw 99 > fallback/payload 0x1b680 payload 361265 > (empty) 0x73a00 null 443544 > mrc.cache 0xdfec0 mrc_cache 65536 > (empty) 0xeff00 null 32664 > bootblock 0xf7ec0 bootblock 32768 > > This is an 8 MB image, I flashed it to SPI flash at address 0. When I boot > the board no output is observed either on USB serial console or on HDMI > display. > > Do I need to add something more to see at least coreboot log. I am tryng > to use GRUB2 as payload to coreboot. > > Thanks > >

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coreboot February 2017