coreboot June 2009

coreboot@coreboot.org

84 participants
500 discussions

Re: [coreboot] ASUS KFN4D16 - K8 FAM10
by thomas ward 06 Aug '09

06 Aug '09

Thanks Myles! Your reply is very helpfull to me (especailly the part about using v2 - I was unsure which of v2 or v3 was appropriate) and very clear. I will follow the "destructions" (probably not till August becasue busy in June and holiday most of July) and once I have blown up the board will post the results to this list. regards, Tom. --- On Wed, 17/6/09, Myles Watson <mylesgw(a)gmail.com> wrote: > From: Myles Watson <mylesgw(a)gmail.com> > Subject: Re: [coreboot] ASUS KFN4D16 - K8 FAM10 > To: "Thomas Ward" <tomwardathome(a)yahoo.co.uk> > Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> > Date: Wednesday, 17 June, 2009, 5:13 PM > > > On Tue, Jun 16, 2009 at 3:36 AM, > Thomas Ward <tomwardathome(a)yahoo.co.uk> > wrote: > > Hello, > > I realise your list is very technical and this is probably > a daft set of question so please forgive me if it is > cluttering up your list but I couldn't find a more > appropriate place to ask,.. > > ... so here goes. > > > > My questions are about running coreboot on an ASUS KFN4-D16 > with an NVIDIA CK804 chipset and a SST SST49LF080A (BIOS?) > chip 33-4C-NHE 0631138-B > > I have 2 cpus one is a 65nm dual core opteron 2210, the > second CPU is a quad core 45nm "Shanghai" opteron > 2376 - this CPU isn't supported by the ASUS BIOS. > > My aim is to get the board to boot with the quad core CPU, > I would be happy if it boots with support for all the RAM > and at least one of the ethernet ports, I can live without > PCI, SATA, USB etc.They should all work. > > > > My plan is to use a BIOS saviour and buy a second > SST49LF080A chip and then > > > > 1. flash coreboot for K8 (?) with flashrom to verify that > coreboot works on this board > > 2. flash coreboot for fam10 (?) with flashrom > > > > does this sound like a good plan?Yes. > > > I have a couple of other questions > > E. what sort of BIOS chip / bios saviour kit should I use > with this board?RD1 > > > > output from flashrom, superiotool and lspci appended > below, > > > > many thanks for any help and good luck with your project, > > > > Tom Ward > > > > root@shed:/home/tom/coreboot/flashrom# ./flashrom > > flashrom v0.9.0-r555 > > No coreboot table found. > > Found chipset "NVIDIA CK804", enabling flash > write... OK. > > Calibrating delay loop... OK. > > Found chip "SST SST49LF080A" (1024 KB) at > physical address 0xfff00000.Hopefully this > chip is socketed. > > > superiotool r3695 > > Found Winbond W83627THF/THG (id=0x82, rev=0x84) at > 0x2eThis SuperIO is supported. > > > 00:00.0 Memory controller: nVidia Corporation CK804 Memory > Controller (rev a4) > > This board is very similar to the > tyan/s2892. > > If I were you, my first step would be to get the BIOS > savior (or just use the pushpin method) > > http://www.coreboot.org/Developer_Manual > > > Once you can recover from a bad flash, > > check out the latest coreboot-v2 > mkdir src/mainboard/asus/kfn4-d16 > svn cp src/mainboard/tyan/s2892/* > src/mainboard/asus/kfn4-d16/ > mkdir targets/asus/kfn4-d16 > > svn cp targets/tyan/s2892/Config.lb targets/asus/kfn4-d16/ > > edit src/mainboard/asus/kfn4-d16/Config.lb > > Enable devices that are in your lspci, disable any that > don't show up. Don't worry about cards that you > plug in, they'll be found automatically. > > Change the SuperIO from chip superio/winbond/w83627hf to > superio/winbond/w83627thf and change any settings there that > you need to. > Change socket_940 to socket_F > > (When you're ready to switch to fam10) > Change amdk8 to amdfam10 everywhere (may need some other > small fixups) > > > edit targets/asus/kfn4-d16/Config.lb > Change s2892 to kfn4-d16 > make sure ROM_SIZE matches the chip you're using. > > > > cd targets > > ./buildtarget asus/kfn4-d16 > > make a payload (Maybe seabios) > cp your_payload targets/asus/kfn4-d16/kfn4-d16/payload.elf > > make -C asus/kfn4-d16/kfn4-d16 > > Last step is to send your patches to the list with a > Signed-off-by: <your-email> line. > > > Thanks, > Myles > > > -----Inline Attachment Follows----- > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

3 2

Dell latitude c610
by CybFr 23 Jul '09

23 Jul '09

Hi, I'd like to re-open a tread from Michal Janke about supporting Dell latitude C610 and its SMSC LPC47N252 SuperIO. - I've found the closest chip from SMSC was FDC37N972, supported by superiotool so I added corresponding entries in smsc.c. - for FDC, UARTS, KBD, RTC, everything seems quite common so I added it in /superio/smsc/smsssuperio/superio.c. (the big difference betweenn supported smsc chips an LPC47N252 is the EC-8051 core... ) What could be the next step ? Thanks for advices -- CybFr

5 14

[flashrom] [PATCH] external serial flasher protocol support
by Urja Rannikko 21 Jul '09

21 Jul '09

Support for an external serial flasher protocol. Supports RS-232, USB serial converters (untested) and TCP streams. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- Please commit my jedec.c readb to readn patch (or carldani's version that i've only heard of in IRC) before this - they're not dependent but without that patch this protocol is awfully slow. Also attached is a simple specification of the protocol this code implements, it hasnt changed much from my last mail, but i attach it here so it's readily available in the same mail with the implementation. I also have the implementation of this protocol on the device side for an Atmel AVR ATmega168 microcontroller, it is also included just for an idea of how i implemented the device side parser - it has GPL headers added to all files and COPYING included to make it GPLv2+ for real, but has not otherwise been looked at for release - the device it runs on is in a way very special, so i think compiling that directly would be of little use to anyone atm. -- urjaman

5 19

sony vaio pcg sr1k
by misi e 21 Jul '09

21 Jul '09

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

5 10

#137: S2895 no function after coreboot 2 flash
by coreboot 15 Jul '09

15 Jul '09

#137: S2895 no function after coreboot 2 flash --------------------------+------------------------------------------------- Reporter: anonymous | Type: defect Status: new | Priority: major Milestone: | Component: buildrom Version: v2 | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Hi Guys, I am not sure whether i am correct here with you guys. But i have some troubles after flashing the tyan-s2895.rom that has been generated with seabios as payload by the buildrom tool. There are no logs in the log folders and everything worked fine. But after flashing the coreboot bios to the board using "flashrom -v -w tyan-s2895.rom" and i "halt" the system, it will come up for a second and switches off immediately. I tried clearing the CMOS, but this did not solve the problem. Any idea what i am doing wrong? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/137> coreboot <http://www.coreboot.org/>

4 32

[PATCH] v3 Resource allocator to v2
by Myles Watson 11 Jul '09

11 Jul '09

This patch series makes v2 more similar to v3. It splits resource allocation into read, compute, allocate. There is no more mutual recursion. They go in this order: 1. white.diff 2. read_first.diff 3. domain_resources.diff 4. constraint.diff 5. compute_allocate.diff It is boot tested on SimNOW and qemu. domain_resources needs to be expanded to include other southbridges and domains. I just wanted early feedback rather than late. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

6 20

[PATCH] flashrom: Flash port parameter for IT87* SPI
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

Add an optional flash port parameter for IT87* SPI controllers in standalone programmer mode. If the parameter is set, the IT87* SPI driver will set the I/O base port of the IT87* SPI controller interface to the port specified in the parameter. Usage: flashrom -p it87spi=port=0x820 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it87spi_force_port/flash.h =================================================================== --- flashrom-it87spi_force_port/flash.h (Revision 634) +++ flashrom-it87spi_force_port/flash.h (Arbeitskopie) @@ -468,6 +468,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); /* it87spi.c */ +extern char *it87opts; extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Index: flashrom-it87spi_force_port/it87spi.c =================================================================== --- flashrom-it87spi_force_port/it87spi.c (Revision 634) +++ flashrom-it87spi_force_port/it87spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> * Copyright (C) 2008 coresystems GmbH * @@ -24,12 +24,14 @@ */ #include <string.h> +#include <stdlib.h> #include "flash.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +char *it87opts = NULL; uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; @@ -56,6 +58,7 @@ static uint16_t find_ite_spi_flash_port(uint16_t port) { uint8_t tmp = 0; + char *portpos = NULL; uint16_t id, flashport = 0; enter_conf_mode_ite(port); @@ -77,6 +80,9 @@ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); printf("LPC write to serial flash %sabled\n", (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ /* If any serial flash segment is enabled, enable writing. */ if ((tmp & 0xe) && (!(tmp & 1 << 4))) { printf("Enabling LPC write to serial flash\n"); @@ -89,6 +95,17 @@ flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); printf("Serial flash port 0x%04x\n", flashport); + if (it87opts && !strlen(it87opts)) { + free(it87opts); + it87opts = NULL; + } + if (it87opts && (portpos = strstr(it87opts, "port="))) { + portpos += 5; + flashport = strtol(portpos, (char **)NULL, 0); + printf("Forcing serial flash port 0x%04x\n", flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } } exit_conf_mode_ite(port); return flashport; Index: flashrom-it87spi_force_port/flashrom.c =================================================================== --- flashrom-it87spi_force_port/flashrom.c (Revision 634) +++ flashrom-it87spi_force_port/flashrom.c (Arbeitskopie) @@ -646,6 +646,8 @@ pcidev_bdf = strdup(optarg + 8); } else if (strncmp(optarg, "it87spi", 7) == 0) { programmer = PROGRAMMER_IT87SPI; + if (optarg[7] == '=') + it87opts = strdup(optarg + 8); } else if (strncmp(optarg, "ft2232spi", 9) == 0) { programmer = PROGRAMMER_FT2232SPI; } else if (strncmp(optarg, "serprog", 7) == 0) { -- http://www.hailfinger.org/ Index: flashrom-it87spi_force_port/flash.h =================================================================== --- flashrom-it87spi_force_port/flash.h (Revision 634) +++ flashrom-it87spi_force_port/flash.h (Arbeitskopie) @@ -468,6 +468,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); /* it87spi.c */ +extern char *it87opts; extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Index: flashrom-it87spi_force_port/it87spi.c =================================================================== --- flashrom-it87spi_force_port/it87spi.c (Revision 634) +++ flashrom-it87spi_force_port/it87spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> * Copyright (C) 2008 coresystems GmbH * @@ -24,12 +24,14 @@ */ #include <string.h> +#include <stdlib.h> #include "flash.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +char *it87opts = NULL; uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; @@ -56,6 +58,7 @@ static uint16_t find_ite_spi_flash_port(uint16_t port) { uint8_t tmp = 0; + char *portpos = NULL; uint16_t id, flashport = 0; enter_conf_mode_ite(port); @@ -77,6 +80,9 @@ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); printf("LPC write to serial flash %sabled\n", (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ /* If any serial flash segment is enabled, enable writing. */ if ((tmp & 0xe) && (!(tmp & 1 << 4))) { printf("Enabling LPC write to serial flash\n"); @@ -89,6 +95,17 @@ flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); printf("Serial flash port 0x%04x\n", flashport); + if (it87opts && !strlen(it87opts)) { + free(it87opts); + it87opts = NULL; + } + if (it87opts && (portpos = strstr(it87opts, "port="))) { + portpos += 5; + flashport = strtol(portpos, (char **)NULL, 0); + printf("Forcing serial flash port 0x%04x\n", flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } } exit_conf_mode_ite(port); return flashport; Index: flashrom-it87spi_force_port/flashrom.c =================================================================== --- flashrom-it87spi_force_port/flashrom.c (Revision 634) +++ flashrom-it87spi_force_port/flashrom.c (Arbeitskopie) @@ -646,6 +646,8 @@ pcidev_bdf = strdup(optarg + 8); } else if (strncmp(optarg, "it87spi", 7) == 0) { programmer = PROGRAMMER_IT87SPI; + if (optarg[7] == '=') + it87opts = strdup(optarg + 8); } else if (strncmp(optarg, "ft2232spi", 9) == 0) { programmer = PROGRAMMER_FT2232SPI; } else if (strncmp(optarg, "serprog", 7) == 0) {

2 2

[PATCH] flashrom: Tarball improvements
by Carl-Daniel Hailfinger 10 Jul '09

10 Jul '09

Change tarball compression from gzip to bzip2. Set the user and group of all files to root. (This is not portable across all tar versions.) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-make_tarball_fix/Makefile =================================================================== --- flashrom-make_tarball_fix/Makefile (Revision 636) +++ flashrom-make_tarball_fix/Makefile (Arbeitskopie) @@ -136,9 +136,9 @@ @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ tarball: export - @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @tar cjf $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 -C $(EXPORTDIR)/ --owner=root --group=root flashrom-$(VERSION)/ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) - @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 .PHONY: all clean distclean dep compiler pciutils features export tarball -- http://www.hailfinger.org/ Index: flashrom-make_tarball_fix/Makefile =================================================================== --- flashrom-make_tarball_fix/Makefile (Revision 636) +++ flashrom-make_tarball_fix/Makefile (Arbeitskopie) @@ -136,9 +136,9 @@ @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ tarball: export - @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @tar cjf $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 -C $(EXPORTDIR)/ --owner=root --group=root flashrom-$(VERSION)/ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) - @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 .PHONY: all clean distclean dep compiler pciutils features export tarball

1 3

msrtool CS5536 interrupt and DIVIL LBAR MSRs
by Peter Stuge 10 Jul '09

10 Jul '09

Can someone please review these register definitions? Thank you! //Peter

4 8

[PATCH] flashrom: Call programmer_shutdown() where needed
by Uwe Hermann 09 Jul '09

09 Jul '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 2

← Newer
1
2
3
4
5
6
7
...
50
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2009